The front end circuit of the new comparator is shown in Fig. 1. The configuration is derived from a Gilbert-type cell [4] with the addition of a conventional long-tailed pair current drive circuit and gain peaking. The input transistors QI and Q2 operate at low collector currents, about 0.5 mA, to ensure a low input bias current without input emitter followers, while the cascode devices Q5 and Q6 reduce Miller effect input capacitance terms. The cross-coupled pair Q3 and Q4 raise the small signal gain to 8.4, while maintaining a 3 dB rolloff frequency over 400 MHz, assisted by the peaking effect of the pole-zero cancellation resistors R3 and R4 [5]. The input configuration has some similarity to that of [6], but by the use of a faster process, and pole-zero cancellation, an improvement factor of 10 has been achieved. This is not without cost, primarily in power, and to some extent in power-delay product. However, in the case of a single comparator this is not usually significant; the criterion applied is absolute speed. An approximate indication of the gain distribution (based on SPICE prediction) is shown in Fig. 2. The stage gain-bandwidth tradeoff was considered very carefully in relation to the rest of the circuit and with respect to the input dynamic range requirement and output configuration. The final choice of gain distribution was arranged for similar rolloff points in each stage, although the limiting factor is the interstage level shift, which introduces both an attenuation and a reduction in bandwidth. Level shifting and the ECL-compatible output stages were essential in this application, but do represent the main speed limitation of the present design; a more desirable configuration would use direct termination of a multiple Gilbert cell array.
The comparator was designed on a 3 um minimum feature size junction isolated bipolar process, a variant of a current 4 Mm production process. A cross section of an n-p-n transistor is shown in Fig. 4. Small geometry devices offer low capacitances with good fT's (greater than 5 GHz) at reasonable current densities. Base width on the process is 0.15 um and emitter depth 0.3 um. Junction isolation offers process simplicity but suffers from higher sidewall capacitance. Circuit variants on an oxide isolated process are under investigation.