`timescale 1us/1us
module clocktest;
reg Clk_in,Rst_in,S1_in,S2_in;
wire Spk_out;
wire[6:0] Display_out;
wire[2:0] Sel_out;
parameter HALF_PERIOD=50;
//产生10KHZ 时钟
initial
begin
Clk_in=0;
forever #HALF_PERIOD Clk_in=~Clk_in; 第十三行
end
//产生复位信号
initial
begin
Rst_in=1;
#(2*HALF_PERIOD) Rst_in=0;
#(10*HALF_PERIOD) Rst_in=1;
end
//产生调节小时信号
initial
begin
S1_in=1;
#(35000*HALF_PERIOD) S1_in=0;
#(60000*HALF_PERIOD) S1_in=1;
end
//产生调节分钟信号
initial
begin
S2_in=1;
#(95000*HALF_PERIOD) S2_in=0;
#(60000*HALF_PERIOD) S2_in=1;
end
clock t(.Spk(Spk_out),.Display(Display_out),.Sel(Sel_out),
.Clk(Clk_in),.Rst(Rst_in), .S1(S1_in),.S2(S2_in));
endmodule
编译后出现
Error (10119): Verilog HDL Loop Statement error at clocktest.v(13): loop with non-constant loop condition must terminate within 250 iterations
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings