Verilog HDL编程有错，谁能帮改下，多谢了。

这是程序谁能帮我看下，多谢了
module sled(seg,s1,clock);
output [7:0] seg;
output [3:0] s1;
input clock;
reg [7:0] seg_reg;
reg [3:0] disp_dat;
reg [36:0] count;
always@(posedge clock)
begin
count=count+1;
end
always
begin
s1_reg=4'b0000;
end
always@(count[16])
begin
disp_dat=count[27:24];
always@(disp_dat)
begin
case(disp_dat)
4'h0:seg_reg=8'hc0;
4'h1:seg_reg=8'hf9;
4'h2:seg_reg=8'ha4;
4'h3:seg_reg=8'hb0;
4'h4:seg_reg=8'h99;
4'h5:seg_reg=8'h92;
4'h6:seg_reg=8'h82;
4'h7:seg_reg=8'hf8;
4'h8:seg_reg=8'h80;
4'h9:seg_reg=8'h90;
4'ha:seg_reg=8'h88;
4'hb:seg_reg=8'h83;
4'hc:seg_reg=8'hc6;
4'hd:seg_reg=8'ha1;
4'he:seg_reg=8'h86;
4'hf:seg_reg=8'h8e;
endcase
end
assign seg=seg_reg;
assign s1=s1_reg;
endmodule
下面是错误信息
Error (10170): Verilog HDL syntax error at sled.v(19) near text "always"; expecting "@", or "end", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequentiaError (10170): Verilog HDL syntax error at sled.v(42) near text "endmodule"; expecting "@", or "end", or an identifier ("endmodule" is a reserved keyword ), or a system task, or "{", or a sequential statementl statement
不知道为什么我有百度文库财富值，这上面无法给。

module sled(seg,s1,clock);
output [7:0] seg;
output [3:0] s1;
input clock;
reg [7:0] seg_reg;
reg [3:0] disp_dat;
reg [36:0] count;
reg [3:0] s1_reg;

always@(posedge clock)begin
count=count+1;
end

always begin
s1_reg=4'b0000;
end

always@(count[16])begin
disp_dat=count[27:24];
end

always@(disp_dat)begin
case(disp_dat)
4'h0:seg_reg=8'hc0;
4'h1:seg_reg=8'hf9;
4'h2:seg_reg=8'ha4;
4'h3:seg_reg=8'hb0;
4'h4:seg_reg=8'h99;
4'h5:seg_reg=8'h92;
4'h6:seg_reg=8'h82;
4'h7:seg_reg=8'hf8;
4'h8:seg_reg=8'h80;
4'h9:seg_reg=8'h90;
4'ha:seg_reg=8'h88;
4'hb:seg_reg=8'h83;
4'hc:seg_reg=8'hc6;
4'hd:seg_reg=8'ha1;
4'he:seg_reg=8'h86;
4'hf:seg_reg=8'h8e;
endcase
end
assign seg=seg_reg;
assign s1=s1_reg;
endmodule

这样改就没错了，但是不知道你这段代码想描述的是什么功能，感觉有些奇怪，所以只能按照语法来这样修改了。

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