verilog编程出现错误 Error (10170): Verilog HDL syntax error at SHUDIAN.v(17) near text "="

module fsm (clk,reset,in,out);
input clk,reset,in;
output out;
reg current_state,next_state;
reg q;

always @(posedge clk)
begin
if(!reset) current_state=s0;
else current_state=next_state;
end
always @(current_state or in or q)
begin
case(current_state)
s0:
out=0;
q=0;
if(in)
begin
next_state=s0;
end
else
begin
next_state=s1;
end
s1:
out=0;
if(q>9999)
begin
next_state=s2;
end
else
begin
q=q+1;
end
s2:
out=0;
q=0;
if(in)
begin
next_state=s0;
end
else
begin
next_state=s3;
end
s3:
out=1;
q=0;
if(!in)
begin
next_state=s3;
end
else
begin
next_state=s4;
end
s4:
out=1;
if(q>9999)
begin
next_state=s5;
end
else
begin
q=q+1;
end
s5:
q=0;
if(in)
begin
next_state=s0;
end
else
begin
next_state=s3;
end
endcase
end
endmodule

Error (10170): Verilog HDL syntax error at SHUDIAN.v(17) near text "="

Error (10170): Verilog HDL syntax error at SHUDIAN.v(28) near text "if"; expecting "endcase", or an identifier ("if" is a reserved keyword ), or a number, or a system task, or "(", or "{", or unary operator

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