Verilog HDL错误求助 Error (10171): Verilog HDL syntax error at ps2_mouse_test.v(88) near end of

Error (10171): Verilog HDL syntax error at ps2_mouse_test.v(88) near end of file ; expecting ".", or an identifier, or "(", or "["

急用!!实在是找不出错误,求高手指点

程序如下:
module ps2_mouse_test(clock,rst_n,ps2_mouse_clk,ps2_mouse_data,sram_data,sram_nwe,sram_noe,sram_addr,sram_ncs,byte3,byte2,byte1,byte0,hsync,vsync,disp_dato);
input clock;
input rst_n;
inout ps2_mouse_clk;
inout ps2_mouse_data;
inout[15:0] sram_data;
output[17:0] sram_addr;
output sram_nwe;
output sram_noe;
output sram_ncs;
output byte3;
output byte2;
output byte1;
output byte0;
output hsync;
output vsync;
output [7:0] disp_dato;
wire clk_100m;
wire clk_25m;
wire wr_ack;
wire wr_req;
wire [18:0] wr_addr;
wire [7:0] wr_data;
wire [9:0] mouse_x;
wire [8:0] mouse_y;
wire left_button;
wire middle_button;
wire right_button;
wire [8:0] x_increment;
wire [8:0] y_increment;
wire datn_ready;
pll pll(
.inclk0(clock),
.c0(clk_100m),
.c1(clk_25m)
);
ps2_mouse_interface ps2_mouse_interface(
.clock(clk_100m),
.reset(~rst_n),
.ps2_clk_in(ps2_mouse_clk),
.ps2_data_in(ps2_mouse_data),
.left_button(left_button),
.right_button(right_button),
.middle_button(middle_button),
.x_increment(x_increment),
.y_increment(y_increment),
.data_ready(data_ready));
count count(
.clock(clk_100m),
.data_ready(data_ready),
.x_inc(x_increment),
.y_inc(y_increment),
.x_addr(mouse_x),
.y_addr(mouse_y));
mouse_test mouse_test(
.clock(clk_100m),
.left_btn(left_button),
.right_btn(right_button),
.middle_btn(mddle_button),
.wr_addr(wr_addr),
.wr_data(wr_data),
.wr_ack(wr_ack),
.wr_req(wr_req));
vga_logic vga_logic(
.ico_wr_clk(clk_100m),
.clk_100m(clk_100m),
.clk_25m(clk_25m),
.vga_clk(),
.vga_reset(~rst_n),
.wr_req( wr_req),
.wr_addr(wr_addr),
.wr_data(wr_data),
.wr_ack(wr_ack),
.sram_nwe(sram_nwe),
.sram_noe(sram_noe),
.sram_addr(sram_addr),
.sram_data(sram_data),
.ico_wr_data(),
.ico_wr_en(1'b0),
.mouse_en(1'b1),
.mouse_x(mouse_x),
.mouse_y(mouse_y),
.hsync(hsync),
.vsync(vsync),
.disp_dato(disp_dato),
.data_enab(data_enab)
);
Endmodule

第1个回答  2011-05-31
Endmodule这里错了啊
verilog是严格区分大小写的
所以编译器不认识Endmodule
只需要改成endmodule就OK了啊~
第2个回答  2011-05-28
ゴω﹋㊣_☆いド→<
现在很多卖家都只是为了赚你的钱,而不把售后当回事。亲要选择好上家哦 。
要是信得过我的话,我们可以交流一下,希望能给你最好的售后,帮助你解决, 我算不上资深的网店卖家,但是凭良心说,不会让你花冤枉钱的。
第3个回答  2011-05-28
Endmodule改成endmodule本回答被提问者采纳
第4个回答  2011-05-30
是语法错误,你再详细看看
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