简单的Verilog HDL程序语法错误问题

//Error (10170): Verilog HDL syntax error at mux2x32.v(21) near text "case"; expecting "endmodule"
//Error (10112): Ignored design unit "mux8x32" at mux2x32.v(7) due to previous errors

module mux2x32 (s, y);
input s;
output y;
assign y = s? 1 : 0;
endmodule

module mux8x32(y0, a0, a1, y1, a2, a3, y2, a4, a5, a6, a7, s0, s1, s2, ans, res);
input [31:0] a0, a1, a2, a3, a4, a5, a6, a7;
input s0, s1, s2;
output y0, y1, y2;
reg y0, y1, y2;
mux2x32 m1 (s0, y0);
mux2x32 m2 (s1, y1);
mux2x32 m3 (s2, y2);
output [2:0] res;
output [31:0] ans;
wire[2:0] res;
assign res[0] = y0;
assign res[1] = y1;
assign res[2] = y2;
case (res)
3'b000:ans = a0;
3'b001:ans = a1;
3'b010:ans = a2;
3'b011:ans = a3;
3'b100:ans = a4;
3'b101:ans = a5;
3'b110:ans = a6;
3'b111:ans = a7;
default : ;
endcase
endmodule
//Error (10170): Verilog HDL syntax error at mux2x32.v(21) near text "case"; expecting "endmodule"
//Error (10112): Ignored design unit "mux8x32" at mux2x32.v(7) due to previous errors