always @(posedge clk_1M) begin
if(count1>=20000 or posedge THR) //待测信号THR上升沿count1=0
count1 <= 0;
else begin
count1 <= count1 + 1;
end
end
always @(negedge THR) begin
width1 <= count1;
det1 <= width1-1000;//THR宽度变化量
end
有
Error (10170): Verilog HDL syntax error at four_pass.v(80) near text "or"; expecting ")"
Error (10170): Verilog HDL syntax error at four_pass.v(82) near text "else"; expecting "end"
两个错误为什么啊?求大神帮助。