[verilog]利用10M的时钟，设计一个单周期形状的周期波形。为什么报错，高手请进！！

module count_top(wave,clk,count);
input clk,count; //可以记数50usoutput wave;
reg [8:0]countreg wave;
always @(posedge clk)
begin if(count<=200) begin wave=0;count=count+1; end else if((count<=300)&&(count>200)) begin wave=1;count=count+1; end else if((count<=500)&&(count>300)) begin wave=0;count=count+1; end else count=0; end
endmodule

结果报错ERROR:HDLCompilers:26 - "count_top.v" line 27 unexpected token: 'reg'