【verilog】利用10M的时钟，设计一个单周期形状的周期波形。为什么报错，高手请进！！
module count_top(clk,wave,rst);
input clk;
input rst;
output wave;
reg wave;
reg [8:0]count;
always @(posedge clk or posedge rst)
begin
if(rst==1)
count<=0;
else
count<=count+1;
begin
if(count<=200)
wave<=0;
else if((count<=300)&&(count>200))
wave<=1;
else if((count<=500)&&(count>300))
wave<=0;
end
end
endmodule
The logic for <wave> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.报错，应该怎么改？谢谢
if(count<=200)
wave<=0;
else if((count<=300)&&(count>200))
wave<=1;
else if((count<=500)&&(count>300))
wave<=0;
end
把这段单拿出来放到一个always块里面试试追问
谢谢，还有一点问题就是，RTL仿真的时候没问题，但是综合后仿真就显示FATAL_ERROR:PersonalityModule:baspmdlm.c:168:1.27 - dll library does not exist.
是哪里有问题呢？在追加你50分吧~
initial
begin
clk = 0;//初始化clock为0
rst = 0;
#20 rst = ~rst;
#20 rst = ~rst;
#10clk = ~clk;
forever
#50clk = ~clk;
end
这个问题是你ISE软件没装好，是11.x的吧！！！？？？？重新安装下试试
