第1个回答 2014-06-11
//第四题verilog代码:(用移位寄存器和组合逻辑实现,moore状态机)
module seq_rec_101_moore(output D_out, input D_in, En, clk, rst);
parameter empty = 3'b000;
reg[2:0] data;
always @(posedge clk)
if(rst == 1)data <= empty;else if(En == 1) data <= {D_in, data[2:1]};
assign D_out = (data == 3'b101);
endmodule
//测试平台
//测试了序列不是101,序列是101两种情况。
module t_seq_rec_101_moore();
reg D_in, En, clk, rst;
wire D_out;
seq_rec_101_moore M0(D_out, D_in, En, clk, rst);
initial #180 $finish;
initial begin #5 rst = 1; #18 rst =0; end
initial begin clk = 0; forever #10 clk = ~clk; end
initial begin #5 En = 1; #100 En = 0;end
initial fork D_in = 0; #25 D_in = 1; #35 D_in = 0; #45 D_in = 1; #55 D_in = 0;
#75 D_in = 1; #95 D_in = 0;
#105 D_in = 1; #115 D_in = 0; #125 D_in = 1; #135 D_in = 0; join
endmodule