Error (10170): Verilog HDL syntax error at verilog3.v(12) near text ","; expecting ")"

module verilog3(clk,ret_n,key1,key2,key3,led1,led2,led3);
input clk;
input rst_n;
input key1,key2,key3;
output led1,led2,led;
reg[2:0] key_rst;

always @(posedge clk or negedge rst_n)
begin
if(!rst_n) key_rst<=3'b111;
else
key_rst <= (key1,key2,key3);
end
reg[2:0] key_rst_r;

always @(posedge clk or negedge rst_n)
begin
if(!rst_n) key_rst_r<=3'b111;
else key_rst_r<=key_rst;
end
wire[2:0] key_an=key_rst_r[2:0]&(~key_rst[2:0]);

reg[19:0] cnt;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) cnt<=20'b0;
else if(key_an) cnt<=20'b0;
else cnt<=cnt+1'b1;

end
reg[2:0] low_aw;

always @(posedge clk or negedge rst_n)
begin
if(!rst_n) low_aw<=3'b111;
else if(cnt==20'hfffff)
low_aw<=(key1,key2,key3);

end
reg[2:0] low_aw_r;

always @(posedge clk or negedge rst_n)
begin
if(!rst_n) low_aw_r<=3'b111;
else low_aw_r<=low_aw;
end
wire[2:0] led_ctrl=low_aw_r[2:0]&(~low_aw[2:0]);

reg l1;
reg l2;
reg l3;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
l1<=1'b0;
l2<=1'b0;
l3<=1'b0;
else
if(led_ctrl[0]) l1<=~l1;
if(led_ctrl[1]) l2<=~l2;
if(led_ctrl[2]) l3<=~l3;
end
assign led1=l1?1'b1:1'b0;
assign led2=l2?1'b1:1'b0;
assign led3=l3?1'b1:1'b0;
endmodule
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